Semiconductor Equipment & Materials

1948

John Bardeen patented an insulated-gate transistor with an inversion layer

Bardeen's IGFET concept forms the conceptual basis of modern MOSFET technology. It set the device target that subsequent fabrication processes and equipment were built to realise.

1955

Carl Frosch and Lincoln Derick accidentally grew a silicon dioxide passivation layer on a silicon wafer at Bell Labs

While working at Bell Telephone Laboratories, Frosch and Derick grew an oxide layer over a silicon wafer and observed surface passivation effects. The discovery underpinned the use of thermal oxidation and oxide masking, which became foundational materials steps in chip fabrication.

1957

Frosch and Derick used masking and predeposition to make the first planar field effect transistors

By 1957 the pair could manufacture silicon dioxide transistors with drain and source adjacent at the same surface. Memos circulated inside Bell Labs before formal publication, and the preprint reached Shockley Semiconductor staff in December 1956, influencing subsequent process invention.

1959

Jean Hoerni invented the planar process at Fairchild Semiconductor

Hoerni, who had received the Frosch and Derick preprint while at Shockley Semiconductor, developed the planar process at Fairchild. The planar process became the organising framework for photolithographic chip fabrication and the equipment built around it.

1960s

Semiconductor device manufacturing spread from Texas and California to Asia, Europe and the Middle East

From its origins in Texas and California in the 1960s, device manufacturing diffused globally. The spread created international demand for fabrication equipment and materials supply chains.

1960–1992

The semiconductor industry scaled wafer diameter from 25 mm to 200 mm over three decades

Wafer size grew from 25 mm in 1960 to 50 mm in 1969, 100 mm in 1976, 125 mm in 1981, 150 mm in 1983 and 200 mm in 1992. Each transition forced redesign of handling, carriers, etch tanks and process tools, and drove the shift from manual tweezers to vacuum wands, cassettes and robotics.

1960s–70s

Etch equipment shifted from wet etching to dry plasma etching

Wet etching was widely used through the 1960s and 1970s before being replaced by dry or plasma etching from the 10 micron to 3 micron nodes. Plasma etch became one of the core equipment categories in chipmaking.

1963

Chih-Tang Sah and Frank Wanlass developed CMOS at Fairchild Semiconductor

CMOS was an improved form of MOSFET technology combining complementary devices. It became the dominant process family for integrated circuits and defined the processing steps equipment makers had to support.

1963

Harold M. Manasevit first documented epitaxial growth of silicon on sapphire

Working at the Autonetics division of North American Aviation, Manasevit documented silicon-on-sapphire epitaxy, publishing with William Simpson in the Journal of Applied Physics in 1964. The technique established a specialist substrate and epitaxial deposition capability.

1965

C.W. Mueller and P.H. Robinson fabricated a MOSFET using the silicon-on-sapphire process at RCA Laboratories

The pair demonstrated that MOSFETs could be built on sapphire substrates. It validated silicon-on-insulator style substrates as a manufacturable materials option.

1968

RCA commercially used CMOS in its 4000-series integrated circuits at a 20 μm process

RCA commercialised CMOS in the late 1960s, beginning production of the 4000 series on a 20 μm process and gradually scaling to 10 μm over the following years. This marked the move of CMOS from laboratory development to volume manufacturing, with many early manufacturers building their own equipment such as ion implanters.

1970s–80s

Chipmakers migrated manufacturing technology from bipolar to MOSFET processes

Several companies switched their semiconductor manufacturing base from bipolar to MOSFET technology during these decades. The migration redirected demand towards oxidation, implantation and CMOS-compatible tooling.

1970s

Doping practice saw ion implantation prevail over thermal diffusion

Initially dopants were introduced by thermal diffusion in furnaces at 900 to 1200 °C, and there was resistance to ion implantation because it still required a separate furnace. Implantation ultimately won out in the 1970s for its better reproducibility, though diffusion persists in silicon photovoltaic cell manufacture.

1978

Semiconductor manufacturing equipment has been considered costly since 1978

From 1978 onwards the capital cost of fabrication equipment became a recognised structural feature of the industry. High tool cost shaped fab economics and concentrated equipment supply among a few vendors.

1980s

Deposition equipment makers saw chemical vapour deposition displace physical vapour deposition as the primary technique

Until the 1980s physical vapour deposition dominated film deposition onto wafers, after which CVD took over. Around the same time diffusion pumps gave way to turbomolecular pumps, which avoid the oil that contaminated wafers in vacuum processing.

1984

KLA developed the first automatic reticle and photomask inspection tool

KLA's tool automated the inspection of reticles and photomasks, previously a manual task. It founded the automated metrology and inspection segment of the equipment industry.

1985

KLA developed an automatic inspection tool for silicon wafers

The tool replaced manual microscope inspection of wafers. Automated wafer inspection became essential to defect control and yield management as feature sizes shrank.

1985

SGS invented the BCD (BCDMOS) process combining bipolar, CMOS and DMOS devices

SGS, now STMicroelectronics, created a process integrating bipolar, CMOS and DMOS devices on one chip. BCDMOS remains a mainstay of power and analogue production, much of it still on 200 mm wafers.

1985

Applied Materials developed the first practical multi-chamber cluster wafer processing tool, the Precision 5000

The Precision 5000 introduced the cluster tool architecture, grouping several process chambers around a shared handler. Cluster tools became the standard configuration for deposition and etch equipment.

June 2026

IBM unveiled the first technology capable of producing chips smaller than 1 nanometre

IBM announced the world's first sub-1 nm chip production technology. The claim marked a further step past the limits of conventional silicon scaling.

April 2025

Fudan University team led by Wenzhong Bao and Peng Zhou announced a 1 nm 32-bit RISC-V chip using 2D semiconductor materials

The Chinese team reported fabricating a working 32-bit RISC-V processor at 1 nm using two-dimensional semiconductor materials. It signalled a materials route beyond silicon for extreme scaling.

2020–23

The global semiconductor industry endured a global chip shortage and a wave of state subsidies

The COVID-19 pandemic triggered a shortage during which manufacturers confined employees to company grounds and counterfeit chips proliferated. Many governments granted subsidies for new fabs, and the US asked TSMC not to produce semiconductors for Huawei, marking semiconductors as a national security matter.

December 2019

TSMC announced an average 5 nm test chip yield of around 80%

TSMC reported about 80% average yield with peak per-wafer yield above 90% for 5 nm test chips of 17.92 mm2 die size. Yield fell to 32% when die size rose to 100 mm2, illustrating the defect sensitivity of advanced nodes.

2019

Samsung and TSMC announced plans to produce 3 nm process nodes

Both leading foundries set out 3 nm roadmaps in 2019. In the same period GlobalFoundries abandoned development beyond 12 nm, judging a sub-12 nm fab beyond its financial means, narrowing the leading edge to a handful of firms.

2018

Samsung began producing the 5 nm process

Samsung started 5 nm production in 2018, while 14 nm and 10 nm chips were in mass production across Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries. TSMC's 5 nm N5 node was reported as the densest, at 171.3 million transistors per square millimetre.

2018

Device researchers proposed GAAFET-based architectures to succeed FinFET

By 2018 numerous candidate structures had been proposed, including horizontal and vertical nanowires, nanosheet transistors such as Samsung MBCFET and Intel Nanoribbon, vertical FETs, complementary and stacked FETs, III-V FinFETs and negative-capacitance FETs. FD-SOI was seen as a lower-cost alternative, each option implying different materials and tool requirements.

2014

Applied Materials proposed the use of cobalt in interconnects at the 22 nm node

Applied Materials advocated encapsulating copper interconnects in cobalt to prevent electromigration, replacing tantalum nitride which must be thicker in that role. It added another speciality metal to the interconnect materials set.

2011

Intel demonstrated FinFET transistors at the 22 nm node

Intel's FinFETs wrapped the gate around three sides of the channel, improving energy efficiency and gate delay as planar transistors succumbed to short channel effects. The architecture required new etch, deposition and metrology capabilities for three-dimensional structures.

2009

Process node naming became a marketing term detached from physical dimensions

Since 2009 the nanometre figure used for a node has had no fixed relation to gate length, metal pitch or gate pitch, having already lost a standardised relation to feature size from 1994. Comparisons such as GlobalFoundries' 7 nm resembling Intel's 10 nm blurred the conventional notion of a node for equipment and materials planning.

2007

Intel introduced high-k/metal gate transistors at the 45 nm node

HKMG replaced polysilicon gates, which had themselves displaced aluminium metal gates in the 1970s. The change brought new high-k dielectric materials and atomic-layer deposition into mainstream logic production; DRAM first adopted the technology in 2015.

2006

Industry roadmappers forecast adoption of 450 mm wafers by 2012 and 675 mm by 2021

In 2006 the expectation was that wafer diameters would continue climbing to 450 mm and then 675 mm. The forecast illustrates how roadmaps for wafer and tool scaling later stalled.

2000

The industry moved to 300 mm wafers and the adoption of FOUPs

300 mm diameter wafers were introduced in 2000, with the transition from 200 mm running through 2001 using bridge tools that handled both sizes. The larger wafers brought sealed FOUP carriers and automated material handling, as manual handling of heavier cassettes had become risky.

1998

Applied Materials introduced the Producer cluster tool with paired isolated chambers

The Producer grouped processing chambers in pairs sharing vacuum and supply lines while remaining otherwise isolated. It was considered revolutionary for raising productivity without sacrificing process quality.

1997

IBM was the first to adopt copper interconnects

IBM introduced copper in place of aluminium for on-chip wiring. Copper metallisation demanded new deposition, plating and polishing equipment and inert handling atmospheres to prevent oxidation.

1995

Chipmakers adopted back-end-of-line metallisation and chemical mechanical polishing

BEoL has been used since 1995 at the 350 nm and 250 nm nodes, and chemical mechanical polishing began to be employed at the same time. CMP became an indispensable planarisation step with its own tool and slurry supply chain.

1990s

Yield engineering shifted its main focus from dust particles to process variation

Historically yield degradation was mainly caused by dust particles, but since the 1990s it has been dominated by process variation and by the tools used in manufacture. Dust nonetheless remains a problem in many older fabs, and killer defects can be as small as a fifth of a feature's width.

1990

The industry adopted 200 mm wafers as the production standard

200 mm diameter wafers were first used in 1990 and remained the standard until 300 mm arrived in 2000. Bridge tools able to process both sizes eased the transition, and 200 mm lines still serve analogue, RF, power, BCDMOS and MEMS products.